Sunday, 7 August 2011

Unix tool : make

The make utility is a software engineering tool for managing and maintaining computer programs.Make  provides most help when the program consists of many component files.
By creating a descriptor file containing dependency rules,macros and suffix rules,you can instruct make to automatically rebuild your program whenever one of the program's component files is modified.

To prepare to use make ,You must write a file called makefile the describes the relationships among files in your program,and the states the commands for updating each file.In a program,typically the executable file is updated from object files to decide which of the file needs to be updated.For each of those files,it issues the commands recorded in the data base.

Simple example:

This is an example descriptor file to build an executable file called prog1.it requires the source file file1.cc,file2.cc,and file3.cc.An include file mydefs.h,is required by files file1.cc and file2.cc.If you wanted to compile this file from the command line using C++ the command would be
        %  CC -o prog1 file1.cc file2.cc file3.cc
This command line is rather long to be entered many times as a program is developed and is prone to typing errors. A descriptor file could run the same command better by using the simple command
    % make prog1
or if prog1 is the first target defined in the descriptor file
    % make
No we are going to see how to write a descriptor file,this example descriptor file is much longer than the necessary but it is useful for describing what is gong on.

prog1 : file1.o file2.o file3.o
        CC -o prog1 file1.o file2.o file3.o
  
file1.o : file1.cc mydefs.h
        CC -c file1.cc
  
file2.o : file2.cc mydefs.h
        CC -c file2.cc
  
file3.o : file3.cc
        CC -c file3.cc
  
clean :
        rm file1.o file2.o file3.o
 


Let's go through the example to see what make does by executing with the command make prog1 and assuming the program has never been compiled.
  1. Make finds the target prog1 and sees that it depends on the object files file1.o file2.o file3.o

  2. make next looks to see if any of the three object files are listed as targets. They are so make looks at each target to see what it depends on. make sees that file1.o depends on the files file1.cc andmydefs.h.

  3. Now make looks to see if either of these files are listed as targets and since they aren't it executes the commands given in file1.o's rule and compiles file1.cc to get the object file.

  4. make looks at the targets file2.o and file3.o and compiles these object files in a similar fashion.

  5. make now has all the object files required to make prog1 and does so by executing the commands in its rule.

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